发明名称 |
Duty ratio correction circuit, double-edged device, and method of correcting duty ratio |
摘要 |
A duty ratio correction circuit, includes: a frequency divider configured to output a second clock signal having a first level that is inverted at a timing of a first edge of a first clock signal and a third clock signal having a second level that is inverted at a timing of a second edge of the first clock signal; phase interpolator configured to generate a fourth clock signal and a fifth clock signal based on phase interpolation of any two of the second clock signal, the third clock signal, a first inverted signal that is obtained by inverting the second clock signal, or a second inverted signal that is obtained by inverting the third clock signal; and a multiplier configured to output an exclusive OR signal of the fourth clock signal and the fifth clock signal as a sixth clock signal. |
申请公布号 |
US8797076(B2) |
申请公布日期 |
2014.08.05 |
申请号 |
US201313907388 |
申请日期 |
2013.05.31 |
申请人 |
Fujitsu Limited |
发明人 |
Kibune Masaya |
分类号 |
H03K3/017 |
主分类号 |
H03K3/017 |
代理机构 |
Arent Fox LLP |
代理人 |
Arent Fox LLP |
主权项 |
1. A duty ratio correction circuit, comprising:
a frequency divider configured to output a second clock signal having a first level that is inverted at a timing of a first edge of a first clock signal and a third clock signal having a second level that is inverted at a timing of a second edge of the first clock signal; a phase interpolator configured to generate a fourth clock signal and a fifth clock signal based on phase interpolation of any two of the second clock signal, the third clock signal, a first inverted signal that is obtained by inverting the second clock signal, or a second inverted signal that is obtained by inverting the third clock signal; and a multiplier configured to output an exclusive OR signal of the fourth clock signal and the fifth clock signal as a sixth clock signal. |
地址 |
Kawasaki JP |