Detection of bad clock conditions

摘要

There is provided a circuit and method for detecting a bad clock condition on a clock signal that includes sampling the value of the clock signal at a first plurality of time delays following a rising edge on the clock signal. This method also includes sampling the value of the clock signal at a second plurality of time delays following a falling edge on the clock signal.

主权项

1. A method of detecting a bad clock condition on a clock signal, the method comprising:
sampling a value of the clock signal at each of a first plurality of time delays timed following an edge of the clock signal to encompass a successive edge of the clock signal; determining whether all of the first plurality of samples have a same logic state; and signaling that the bad clock condition exists if all of the first plurality of samples have the same logic state.