发明名称 Software application performance enhancement
摘要 Generating parallelized executable code from input code includes statically analyzing the input code to determine aspects of data flow and control flow of the input code; dynamically analyzing the input code to determine additional aspects of data flow and control flow of the input code; generating an intermediate representation of the input code based at least in part on the aspects of data flow and control flow of the input code identified by the static analysis and the additional aspects of data and control flow of the input code identified by the dynamic analysis; and processing the intermediate representation to determine portions of the intermediate representation that are eligible for parallel execution; and generating parallelized executable code from the processed intermediate representation.
申请公布号 US8799884(B2) 申请公布日期 2014.08.05
申请号 US200912583188 申请日期 2009.08.13
申请人 QUALCOMM Incorporated 发明人 Dreyer Robert Scott;Jones Joel Kevin;Sharp Michael Douglas;Baev Ivan Dimitrov
分类号 G06F9/45;G06F9/30 主分类号 G06F9/45
代理机构 代理人 Cole Nicholas A.
主权项 1. A system for generating parallelized executable code from input code, comprising: a plurality of processors configured to: statically analyze the input code to determine aspects of data flow and control flow of the input code, the input code comprising binary code of an application program designed for single core processing, wherein statically analyze the input code further includes a processor inserting instrumenting code within the input code, the instrumenting code facilitating instrumentation of runtime information;dynamically analyze the input code to determine additional aspects of data flow and control flow of the input code, wherein dynamically analyze the input code includes executing the instrumenting code;generate an intermediate representation of the input code based at least in part on the aspects of data flow and control flow of the input code identified by the static analysis and the additional aspects of data and control flow of the input code identified by the dynamic analysis;process the intermediate representation to determine portions of the intermediate representation that may be eligible for parallel execution; andgenerate parallelized executable code based on the intermediate representation and the input code and that is capable of being executed by the plurality of processors; and one or more memories coupled to the plurality of processors, configured to provide the plurality of processors with instructions.
地址 San Diego CA US