Software selectable adjustment of SIMD parallelism

摘要

Selective power control of one or more processing elements matches a degree of parallelism to requirements of a task performed in a highly parallel programmable data processor. For example, when program operations require less than the full width of the data path, a software instruction of the program sets a mode of operation requiring a subset of the parallel processing capacity. At least one parallel processing element, that is not needed, can be shut down to conserve power. At a later time, when the added capacity is needed, execution of another software instruction sets the mode of operation to that of the wider data path, typically the full width, and the mode change reactivates the previously shut-down processing element.

主权项

1. A non-transitory computer-readable storage medium comprising code, which when executed by a processor, causes the processor to perform operation for processing a SIMD instruction in a SIMD data processor when a width of a data path required by the SIMD instruction is greater than a width of an active data path, comprising:
code for executing one or more operations in parallel in at least two arithmetic logic units of the data processor, so as to process data of a first width; upon execution of a mode change instruction, code for placing a first one of the at least two arithmetic units into a reduced power state; and while the first arithmetic logic unit is in the reduced power state, code for executing one or more instructions in a second one of the at least two arithmetic units, so as to process data of a second width smaller than the first width; code for receiving a SIMD instruction calling for processing of data of the first width; code for expanding the SIMD instruction in response to the received SIMD instruction calling for processing of data of the first width to at least two instructions calling for processing of data of the second width; and code for executing the at least two instructions resulting from expansion in sequence through the second arithmetic logic unit.