| 发明名称 | Power-on reset circuit | ||
| 摘要 | The power-on reset circuit includes: a NMOS transistor having a source connected to a second power supply terminal and a gate connected to a drain thereof; a depletion-type NMOS transistor having a source connected to the drain of the NMOS transistor, a drain connected to a first power supply terminal and a gate connected to the second power supply terminal; a PMOS transistor having a source connected to the first power supply terminal, a gate connected to the drain of the NMOS transistor and a drain; a capacitor having one end connected to the drain of the PMOS transistor and the other end connected to the second power supply terminal; and a waveform shaping circuit having an input terminal connected to the drain of the PMOS transistor and an output terminal from which a power-on reset signal is output. | ||
| 申请公布号 | US8797070(B2) | 申请公布日期 | 2014.08.05 |
| 申请号 | US201313750456 | 申请日期 | 2013.01.25 |
| 申请人 | Seiko Instruments Inc. | 发明人 | Oka Tomohiro |
| 分类号 | H03L7/00;H03K17/22 | 主分类号 | H03L7/00 |
| 代理机构 | Brinks Gilson & Lione | 代理人 | Brinks Gilson & Lione |
| 主权项 | 1. A power-on reset circuit, comprising: a NMOS transistor having a source connected to a second power supply terminal and a gate connected to a drain thereof; a depletion-type NMOS transistor having a source connected to the drain of the NMOS transistor, a drain connected to a first power supply terminal and a gate connected to the second power supply terminal; a PMOS transistor having a source connected to the first power supply terminal, a gate connected to the drain of the NMOS transistor and a drain; a capacitor having one end connected to the drain of the PMOS transistor and the other end connected to the second power supply terminal; and a waveform shaping circuit having an input terminal connected to the drain of the PMOS transistor and an output terminal from which a power-on reset signal is output. | ||
| 地址 | Chiba JP | ||