PHOTOELECTRIC SENSOR AND PHOTOELECTRIC TOUCH PANEL

摘要

A photoelectric sensor, comprising: a first thin film transistor (T1) for converting a photo signal into an electrical signal; a second thin film transistor (T2) for performing an integration operation on the electrical signal; a third thin film transistor (T3) for reading the electrical signal; and a first capacitor (C1) for storing an energy of the electrical signal, wherein a drain electrode of the first thin film transistor (T1) is connected to one end of the first capacitor (C1) and a source electrode of the third thin film transistor (T3); a source electrode of the first thin film transistor (T1) is connected to a drain electrode of the second thin film transistor (T2); a gate electrode of the first thin film transistor (T1) is supplied with a bias signal; wherein a gate electrode of the second thin film transistor (T2) is supplied with an integration signal; a source electrode of the second thin film transistor (T2) is connected to a high level end of a power source; the other end of the first capacitor (C1) is connected to a low level end of the power source; and wherein a gate electrode of the third thin film transistor (T3) is supplied with a scan signal; a drain electrode of the third thin film transistor (T3) is configured to output the read electrical signal.

主权项

1. A photoelectric sensor, comprising:
a first thin film transistor (T1) for converting a photo signal into an electrical signal; a second thin film transistor (T2) for performing an integration operation on the electrical signal; a third thin film transistor (T3) for reading the electrical signal; and a first capacitor (C1) for storing an energy of the electrical signal, wherein a drain electrode of the first thin film transistor (T1) is connected to one end of the first capacitor (C1) and a source electrode of the third thin film transistor (T3); a source electrode of the first thin film transistor (T1) is connected to a drain electrode of the second thin film transistor (T2); a gate electrode of the first thin film transistor (T1) is supplied with a bias signal; wherein a gate electrode of the second thin film transistor (T2) is supplied with an integration signal; a source electrode of the second thin film transistor (T2) is connected to a high level end of a power source; the other end of the first capacitor (C1) is connected to a low level end of the power source; and wherein a gate electrode of the third thin film transistor (T3) is supplied with a scan signal; a drain electrode of the third thin film transistor (T3) is configured to output the read electrical signal.