| 摘要 |
<p>The present invention reduces the mounting area of a semiconductor memory used for applications which do not require a high-speed read operation, and moderates an increase in test cost. A semiconductor memory (1) is provided with a pluralit y of word lines, a plurality of bit line pairs, a plurality of memory cells (41) provided corresponding to intersecting sections of the plurality of word lines and the plurality of bit line pairs, a plurality of pre-charge circuits (21a, 21b) provided corresponding to each bit line pair, and a plurality of readout circuits (23) provided corresponding to each bit line pair. In the semiconductor memory (1), a write to and a read from the plurality of memory cells are performed in accordance with a clock signal. Furthermore, in the semiconductor memory (1), a write is performed within a single cycle of the clock signal, and a read is performed throughout a read cycle equivalent to a plurality of clock signal cycles.</p> |
