NONVOLATILE MEMORY BITCELL

摘要

A multiple time programmable nonvolatile memory device having a single polysilicon memory cell includes a select transistor and a bitcell transistor. The bitcell transistor has asymmetrically configured source, drain, and channel regions including asymmetrically configured source-body and drain-body junctions. Compared with the drain-body junction, the impurity concentration gradient of the source-body junction is more gradual, which may significantly improve program disturb immunity. The bitcell transistor gate may be connected to an electrode of a coupling capacitor, but may be otherwise floating or Ohmically isolated. The floating gate of the bitcell is protected by a dielectric layer for potentially improved data retention.

主权项

1. A method, comprising:
forming a select transistor gate overlying a select transistor channel region of a substrate, the select transistor channel region laterally positioned between a select transistor source region and a select transistor drain region; forming a bitcell transistor gate overlying a bitcell transistor channel region of the substrate; forming a proximal drain region of the bitcell transistor adjacent to the bitcell transistor channel region, wherein the proximal drain region forms a drain-body junction with a transistor body of the bitcell transistor; and forming a bitcell transistor source region adjacent to the bitcell transistor channel region, wherein the bitcell transistor source region forms a source-body junction with the transistor body; wherein an impurity concentration gradient of the drain-body junction is greater than an impurity concentration gradient of the source-body junction.