SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME

摘要

PROBLEM TO BE SOLVED: To inhibit over etching of a device isolation insulation film and an impurity diffusion layer in a contact structure having a large aspect ratio in an LSI device on which a DRAM cell and a logic are mounted in a mixed manner, thereby inhibiting bonding leakage.SOLUTION: An etching stopper layer 121 covering a peripheral MOS transistor, and a second etching stopper layer 122 above a capacitor part of a DRAM memory cell are formed. Each of impurity diffusion layers 113 of the peripheral MOS transistor is connected with a metal wiring layer formed above the capacitor part by an electrode layer 131 penetrating through the first and the second etching stopper layers 121 and 122. At least one of the impurity diffusion layers 113 connects the electrode layer 131 onto a boundary of the device isolation insulation film 102, and an electrode layer 131 bottom part formed on the device isolation insulation film 102 has a depth from a surface of the impurity diffusion layer 113 shorter than a junction depth of the impurity diffusion layer 113.