Multiport Memory Architecture

摘要

The present disclosure describes techniques and apparatuses for multiport memory architecture. In some aspects serial data is received from a data port and converted to n-bit-wide words of data. The n-bit-wide words of data are then buffered as a k-word-long block of parallel data into a line of a multiline buffer as a block of k*n bits of data. The block of k*n bits of data is then transmitted to a multiport memory via a write bus effective to write the block of k*n bits of data to the multiport memory.

主权项

1. A method comprising:
converting, at a first frequency, serial data received from a data port to n-bit-wide words of parallel data; buffering a k-word-long block of the n-bit-wide words of parallel data into a line of a port buffer as k*n bits of data by sequentially writing k words of the n-bit-wide words of parallel data into k data storage elements of the line of the port buffer; and transmitting, at a second frequency, the k*n bits of data to a memory array via a write bus effective to write the k*n bits of data to the memory array, the second frequency different from the first frequency.