INTEGRATED TEST CIRCUIT AND METHOD FOR MANUFACTURING AN INTEGRATED TEST CIRCUIT

摘要

An integrated test circuit, including a plurality of test structure elements, wherein each test structure element includes at least a supply line and a test line; a plurality of select transistors, wherein each select transistor is assigned to one corresponding test structure element, and wherein each select transistor includes a first controlled region, a second controlled region, and a control region, wherein the second controlled region of each select transistor is respectively connected to the supply line of the corresponding test structure element, so that each select transistor is unambiguously assigned to the corresponding test structure element; and a plurality of contact pads, connected to respective first controlled regions and control regions of the plurality of select transistors, such that each test structure element of the plurality of test structure elements can be individually addressed by the plurality of contact pads.

主权项

1. An integrated test circuit, comprising:
a plurality of test structure elements, wherein each test structure element of the plurality of test structure elements comprises at least one supply line and at least one test line; a plurality of select transistors, wherein each select transistor of the plurality of select transistors is assigned to one corresponding test structure element, and wherein each select transistor of the plurality of select transistors comprises a first controlled region, a second controlled region, and a control region, wherein the second controlled region of each select transistor of the plurality of select transistors is respectively electrically connected to the supply line of the corresponding test structure element, so that each select transistor is unambiguously assigned to the corresponding test structure element; a plurality of contact pads, wherein each contact pad of a first set of contact pads of the plurality of contact pads is respectively electrically connected to the control region of corresponding select transistors, and wherein each contact pad of a second set of contact pads of the plurality of contact pads is respectively electrically connected to the first controlled region of corresponding select transistors, so that each select transistor is unambiguously assigned to respectively two contact pads of the plurality of contact pads and each test structure element of the plurality of test structure elements can be individually addressed by the plurality of contact pads.