DECOUPLED LOCKING DMA ARCHITECTURE

摘要

A decoupled Direct Memory Access (DMA) architecture includes at least two DMA controllers, and optionally at least one of the DMA controllers is operable to assert a lock signal operable to selectively inhibit write access to at least a portion of one system data storage element. The DMA controllers are optionally operable to communicate pending task information and to reschedule pending tasks of at least one the DMA controllers. Optionally data is transferred from at least a first one of the DMA controllers to one or more function units, and processed data from the function units is provided to at least a second one of the DMA controllers. Optionally the DMA controllers and one or more memory elements accessible to the DMA controllers are implemented as part of an I/O device.

主权项

1. A system comprising:
a read DMA coupled between a first buffer memory and a function unit; a write DMA coupled between the function unit and a second buffer memory; wherein the read DMA is enabled to send to the function unit a header according to a read DMA command followed by data read from the first buffer memory according to the read DMA command, the header comprising function unit control information and a length field specifying a length of the data read from the first buffer memory and sent to the function unit; wherein the function unit is operable to transform the data read from the first buffer memory according to the function unit control information; and wherein the write DMA is enabled to write the transformed data from the function unit into the second buffer memory.