| 发明名称 |
SIGNAL PROCESSING CIRCUIT AND METHOD |
| 摘要 |
A signal processing circuit includes a PLL circuit configured to lock to a frequency contained in an input signal, a signal generating circuit configured to detect a direct-current component of a signal that is obtained by shifting frequencies of the input signal by a displacement equal to the locked frequency, and to generate a signal that has an amplitude responsive to the detected direct-current component and that has the same frequency and phase as a signal component of the locked frequency of the input signal, and a subtraction circuit configured to subtract the signal generated by the signal generating circuit from the input signal. |
| 申请公布号 |
US2014211899(A1) |
申请公布日期 |
2014.07.31 |
| 申请号 |
US201314082918 |
申请日期 |
2013.11.18 |
| 申请人 |
FUJITSU LIMITED |
发明人 |
FURUDATE Hideki |
| 分类号 |
H04L7/033 |
主分类号 |
H04L7/033 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A signal processing circuit, comprising:
a PLL circuit configured to lock to a frequency contained in an input signal; a signal generating circuit configured to detect a direct-current component of a signal that is obtained by shifting frequencies of the input signal by a displacement equal to the locked frequency, and to generate a signal that has an amplitude responsive to the detected direct-current component and that has the same frequency and phase as a signal component of the locked frequency of the input signal; and a subtraction circuit configured to subtract the signal generated by the signal generating circuit from the input signal. |
| 地址 |
Kawasaki-shi JP |
