SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

摘要

PROBLEM TO BE SOLVED: To provide an SRAM which achieves both an SNM and a write-in margin even at a low power source voltage.SOLUTION: The SRAM includes: cell power source lines provided corresponding to first and second columns; a power source line supplying a power source voltage; and first and second power source circuits which are provided corresponding to the cell power source lines of the first and second columns, and electrically connect between corresponding memory cell power source lines and the power source lines. Each of the memory cells is constituted by a CMOS latch circuit having first and second P-channel type transistors, first to fourth N-channel type transistors, and first and second storage nodes. The first power source circuit lowers a voltage of a first memory cell power source line in response to a signal selecting the first column during writing, and the second power source circuit lowers a voltage of a second memory cell power source line in response to a signal selecting the second column during writing.