TECHNIQUES FOR ENHANCING FRACTURE RESISTANCE OF INTERCONNECTS

摘要

Techniques and structure are disclosed for enhancing fracture resistance of back-end interconnects and other such interconnect structures by increasing via density. Increased via density can be provided, for example, within the filler/dummified portion(s) of adjacent circuit layers within a die. In some cases, an electrically isolated (floating) filler line of an upper circuit layer may include a via which lands on a floating filler line of a lower circuit layer in a region corresponding to where the filler lines cross/intersect. In some such cases, the floating filler line of the upper circuit layer may be formed as a dual-damascene structure including such a via. In some embodiments, a via similarly may be provided between a floating filler line of the upper circuit layer and a sufficiently electrically isolated interconnect line of the lower circuit layer. The techniques/structure can be used to provide mechanical integrity for the die.

主权项

1. An integrated circuit comprising:
a first circuit layer including a first filler line; and a second circuit layer adjacent to the first circuit layer, the second circuit layer including a second filler line, wherein the second filler line includes a first anchoring structure which anchors the second filler line to the first filler line.