Buried metal-semiconductor alloy layers and structures and methods for fabrication thereof

摘要

A method for forming a metal-semiconductor alloy layer uses particular thermal annealing conditions to provide a stress free metal-semiconductor alloy layer through interdiffusion of a buried semiconductor material layer and a metal-semiconductor alloy forming metal layer that contacts the buried semiconductor material layer within an aperture through a capping layer beneath which is buried the semiconductor material layer. A resulting semiconductor structure includes the metal-semiconductor alloy layer that further includes an interconnect portion beneath the capping layer and a contiguous via portion that penetrates at least partially through the capping layer. Such a metal-semiconductor alloy layer may be located interposed between a substrate and a semiconductor device having an active doped region.

主权项

1. A microelectronic structure comprising a metal silicide consisting essentially of a semiconductor element and a metal element selected from the group consisting of nickel, cobalt, iron, titanium, tungsten, erbium, ytterbium, platinum, vanadium, and combinations thereof, the metal silicide located interposed between a buried dielectric layer of a substrate and a dielectric capping layer, the metal silicide comprising an interconnect portion of a single material layer beneath the capping layer and two via portions that are contiguous with the interconnect portion and penetrating through the capping layer, wherein one of the two via portions is present at each end of the interconnect portion, wherein at least the interconnect portion of the metal silicide is free of stress and wherein an entirety of a bottommost surface of said interconnect portion of said metal silicide is in direct contact with an uppermost surface of said buried dielectric layer of a substrate.