Low cost high voltage power FET and fabrication

摘要

A power field effect transistor (FET) is disclosed which is fabricated in as few as six photolithographic steps and which is capable of switching current with a high voltage drain potential (e.g., up to about 50 volts). In a described n-channel metal oxide semiconductor (NMOS) embodiment, a drain node includes an n-well region with a shallow junction gradient, such that the depletion region between the n-well and the substrate is wider than 1 micron. Extra photolithographic steps are avoided using blanket ion implantation for threshold adjust and lightly doped drain (LDD) implants. A modified embodiment provides an extension of the LDD region partially under the gate for a longer operating life.

主权项

1. A method of forming an integrated circuit including a drain extended metal oxide semiconductor (MOS) field effect transistor (FET), comprising:
providing a substrate of given conductivity type having an isolated active area including source, drain, channel and substrate contact regions; performing a selective first implant through a patterned mask of dopant of opposite conductivity type, to form a well in a portion of the drain region laterally spaced from the channel region; performing a blanket threshold adjust second implant of dopant of the given conductivity type into the source region, into the drain region including into the well, into the channel region and into the substrate contact region; forming a gate structure over the channel region; after forming the gate structure, performing a blanket lightly doped drain third implant of dopant of the opposite conductivity type into the source region, into the drain region including into the well and into the substrate contact region, to form a lightly doped drain region in the drain region extending laterally beyond the well toward the channel region; performing a selective fourth implant through a patterned mask of dopant of the opposite conductivity type, to form a source adjacent to the channel region in the source region and a drain laterally spaced from the channel region within the well in the drain region; performing a selective fifth implant through a patterned mask of dopant of the given conductivity type, to form a substrate contact area in the substrate contact region; forming a pre-metal dielectric layer over the substrate; and forming conductive contacts through the pre-metal dielectric layer to the source, the drain, the gate structure and the substrate contact area; wherein the isolated active area is defined by forming oxide isolation elements in the substrate; and wherein forming the oxide isolation elements includes forming a nitride layer over the substrate prior to performing the selective first implant; and, after performing the selective first implant, forming field oxide isolation elements in the substrate by thermal growth in regions where the nitride layer has been removed, the implanted dopant of opposite conductivity type in the well region thermally diffusing during the thermal growth.