Techniques for electromigration stress determination in interconnects of an integrated circuit

摘要

In one or more embodiments, one or more methods, processes, and/or systems described can determine stress failures in interconnect segments of integrated circuit designs and correct those failure via modifying the interconnect segments of the integrated circuit designs with one or more additions to the interconnect segments of the integrated circuit designs. Potentials can be received from a simulation, and one or more failures of an interconnect segment can be determined via the potentials from the simulation. For example, a failure can be determined via a comparison with a potential from the simulation and a critical potential. An interconnect segment can be modified with a stub such that a comparison with a potential from the simulation and a critical potential to provide a non-failing, modified interconnect segment.

主权项

1. A method, comprising:
generating, using a data processing system, a directed graph that represents an interconnect segment of an integrated circuit design; determining, using the data processing system, a highest potential node of nodes of the directed graph that represents the interconnect segment; determining, using the data processing system, a lowest potential node of the nodes of the directed graph that represents the interconnect segment; calculating, using the data processing system, a potential difference between a first potential associated with the highest potential node and a second potential associated with the lowest potential node; determining, using the data processing system, if the potential difference is less than one half of a critical potential difference; and if the potential difference is less than one half of the critical potential difference, indicating, using the data processing system, that the interconnect segment of the integrated circuit design passes.