Providing row redundancy to solve vertical twin bit failures

摘要

A circuit includes a failure address register configured to store a first row address, a row address modifier coupled to the failure address register, wherein the row address modifier is configured to modify the first row address received from the failure address register to generate a second row address. A first comparator is configured to receive and compare the first row address and a third row address. A second comparator is configured to receive and compare the second row address and the third row address. The first and the second row addresses are failed row addresses in a memory.

主权项

1. A circuit comprising:
a first comparator comprising a first input configured to receive a first row address of a memory, and a second input configured to receive a second row address of the memory, wherein the first comparator is configured to compare the first and the second row addresses and output a first comparison result; a failure address register configured to store the second row address, wherein the failure address register is coupled to the first comparator; a row address modifier coupled to the failure address register, wherein the row address modifier is configured to modify the second row address received from the failure address register to generate a third row address; and a second comparator comprising a first input configured to receive the third row address from the row address modifier, and a second input configured to receive the first row address, wherein the second comparator is configured to compare the first and the third row addresses and output a second comparison result.