Stack package and semiconductor package including the same

摘要

A stack package usable in a three-dimensional (3D) system-in-package (SIP) includes a first semiconductor chip, a second semiconductor chip, and a supporter. The first semiconductor chip includes a through silicon via (TSV), and the second semiconductor chip is stacked on the first semiconductor chip and is electrically connected to the first semiconductor chip through the TSV of the first semiconductor chip. The supporter is attached onto the first semiconductor chip so as to be spaced apart from an edge of the second semiconductor chip.

主权项

1. A stack package comprising:
a first semiconductor chip comprising a through silicon via (TSV); a second semiconductor chip that is stacked on a first surface of the first semiconductor chip and is electrically connected to the first semiconductor chip through the TSV of the first semiconductor chip; a supporter that is attached onto the first surface of the first semiconductor chip so as to be spaced apart from an edge of the second semiconductor chip; and a molding member that covers an upper surface of the first semiconductor chip so as to seal the second semiconductor chip and the supporter, wherein the supporter comprises a material having a Young's modulus greater than a Young's modulus of the molding member and smaller than a Young's modulus of the first semiconductor chip.