Circuit for selectively providing maximum or minimum of a pair of floating point operands

摘要

A floating point max/min circuit for determining the maximum or minimum of two floating point operands includes a first analysis circuit configured to determine a format of a first floating point operand of the two floating point operands based upon floating point status information encoded within the first floating point operand, a second analysis circuit configured to determine a format of a second floating point operand of the two floating point operands based upon floating point status information encoded within the second floating point operand, a decision circuit, coupled to the first analysis circuit and to the second analysis circuit and responding to a function control signal that indicates the threshold condition is one of a maximum of the two floating point operands and a minimum of the two floating point operands, for generating at least one assembly control signal based on the format of a first floating point operand, the format of a second floating point operand, and the function control signal, and a result assembler circuit, coupled to the decision circuit, for producing a result indicating which of the first floating point operand and the second floating point operand meet the threshold condition, based on the at least one assembly control signal. The format of the floating point operands may be from a group comprising: not-a-number (NaN), positive infinity, negative infinity, normalized, denormalized, positive overflow, negative overflow, positive underflow, negative underflow, inexact, exact, division by zero, invalid operation, positive zero, and negative zero. The result produced may be a third floating point operand having encoded floating point status information, and at least part of the encoded floating point status information in the result may come from either the first floating point operand or the second floating point operand.

主权项

1. A method for providing one of the maximum and the minimum of a first floating point operand and a second floating point operand, comprising:
receiving the first floating point operand in a first operand buffer; receiving the second floating point operand in a second operand buffer; determining, using a first analysis circuit, a first format of the first floating point operand based upon floating point status information encoded within the first floating point operand; determining, using a second analysis circuit, a second format of the second floating point operand based upon floating point status information encoded within the second floating point operand; and producing a result indicating which of the first floating point operand and the second floating point operand is larger or smaller than the other, based on the first format and the second format.