Phase-locked loop and method for clock delay adjustment

摘要

A phase-locked loop (PLL) for clock delay adjustment and a method thereof are disclosed. The method includes the following steps. A reference clock signal and a clock signal are generated. The reference clock signal is fed through an N-divider to generate an output clock signal having a frequency 1/N of the reference clock signal. In a phase frequency detector, a control signal is generated in accordance with a phase difference and a frequency difference between the output clock signal and a feedback signal generated by a voltage controlled oscillator coupled to the phase frequency detector. The control signal is then fed through a charge pump and a loop filter to generate a voltage control signal according to the control signal. Moreover, in an adjustable delay element, a blended delay signal is generated according to a clock signal and the voltage control signal.

主权项

1. A phase-locked loop with an adjustable delay element for clock delay adjustment, comprising:
an N-divider receiving a reference clock signal and generating an output clock signal having a frequency 1/N of the reference clock signal; a phase frequency detector generating a control signal according to a phase difference and a frequency difference between the output clock signal and a feedback signal; a charge pump receiving the control signal of the phase frequency detector; a loop filter coupled to the charge pump for generating a voltage control signal according to the control signal of the phase frequency detector; a voltage controlled oscillator coupled to the phase frequency detector and transmitting the feedback signal to the phase frequency detector; and an adjustable delay element generating a blended delay signal according to a clock signal and the voltage control signal, wherein the adjustable delay element comprises:
a delay array receiving the clock signal and generating a delay signal according to the clock signal and the voltage control signal; anda delay blender receiving the delay signal from the delay array and generating a blended delay signal according to the clock signal and the delay signal,wherein the blended delay signal generated by the delay blender has a phase difference between the clock signal and the delay signal, and the phase difference is selected among a plurality of steps according to the delay signal generated by the delay array.