发明名称 Method of manufacturing thin film transistor, thin film transistor manufactured by using the method, method of manufacturing organic light-emitting display apparatus, and organic light-emitting display apparatus manufactured by using the method
摘要 A method of manufacturing a thin film transistor (TFT), a TFT manufactured by the method, a method of manufacturing an organic light-emitting display apparatus that includes the TFT, a display including the TFT. By including a buffer layer below and an insulating layer above a silicon layer for the TFT, the silicon layer can be crystallized without being exposed to air, so that contamination can be prevented. Also, due to the overlying insulating layer, the silicon layer can be patterned without directly contacting photoresist. The result is a TFT with uniform and improved electrical characteristics, and an improved display apparatus.
申请公布号 US8791032(B2) 申请公布日期 2014.07.29
申请号 US201113200383 申请日期 2011.09.23
申请人 Samsung Display Co., Ltd. 发明人 Park Byoung-Keon;Park Jong-Ryuk;Lee Dong-Hyun;Seo Jin-Wook;Lee Ki-Yong
分类号 H01L29/18 主分类号 H01L29/18
代理机构 代理人 Bushnell, Esq. Robert E.
主权项 1. A method of manufacturing a thin film transistor (TFT), the method comprising the steps of: forming a buffer layer, an amorphous silicon layer, and an insulating layer on a substrate; crystallizing the amorphous silicon layer as a polycrystalline silicon layer; forming a semiconductor layer and a gate insulating layer which have a predetermined shape by simultaneously patterning the polycrystalline silicon layer and the insulating layer; forming a gate electrode including a first portion and a second portion by forming and patterning a metal layer on the gate insulating layer, wherein the first portion is formed on the gate insulating layer and overlapped with a channel region of the semiconductor layer, and wherein the second portion contacts the semiconductor layer; forming a source region and a drain region on the semiconductor layer by performing doping on a region of the semiconductor layer, wherein the region does not include the channel region overlapping the gate electrode and constitutes a region which does not overlap the gate electrode; forming an interlayer insulating layer on the gate electrode so as to cover the gate insulating layer; forming contact holes on the interlayer insulating layer and the gate insulating layer so as to expose the source region and the drain region, and simultaneously forming an opening for exposing the second portion; and forming a source electrode and a drain electrode by forming and patterning a conductive layer on the interlayer insulating layer, wherein the source electrode and the drain electrode are electrically connected to the source region and the drain region, respectively, via the contact holes, and simultaneously removing the second portion exposed via the opening.
地址 Giheung-Gu, Yongin, Gyeonggi-Do KR