Memory system and method using stacked memory device dice, and system using the memory system

摘要

A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that is operable to control the timing at which the logic die receives signals, such as read data signals, from each of the memory device dice. The timing correction controls the timing of the read data or other signals by adjusting the timing of respective strobe signals, such as read strobe signals, that are applied to each of the memory device dice. The memory device dice may transmit read data to the memory device at a time determined by when it receives the respective strobe signals. The timing of each of the strobe signals is adjusted so that the read data or other signals from all of the memory device dice are received at the same time.

主权项

1. An apparatus, comprising:
a timing control circuit configured to provide a plurality of data strobe signals and a plurality of timing control signals; a plurality of strobe timing adjustment circuits, a strobe timing adjustment circuit of the plurality of strobe timing adjustment circuits configured to receive a data strobe signal of the plurality of data strobe signals and a timing control signal of the plurality of timing control signals, the strobe timing adjustment circuit of the plurality of strobe timing adjustment circuits further configured to provide an adjusted clock signal based, at least in part, on the timing control signal of the plurality of timing control signals and to provide the data strobe signal of the plurality of data strobe signals in accordance with the adjusted clock signal.