Vertical type integrated circuit devices and memory devices including conductive lines supported by Mesa structures and methods of fabricating the same

摘要

A vertical type integrated circuit device includes a substrate and a pillar vertically protruding from the substrate. The pillar includes a lower impurity region and an upper impurity region therein and a vertical channel region therebetween. A portion of the pillar including the lower impurity region therein includes a mesa laterally extending therefrom. The device further includes a first conductive line extending on a first sidewall of the pillar and electrically contacting the lower impurity region, and a second conductive line extending on a second sidewall of the pillar adjacent the vertical channel region. The second conductive line extends in a direction perpendicular to the first conductive line and is spaced apart from the mesa. Related devices and methods of fabrication are also discussed.

主权项

1. A vertical type integrated circuit device comprising:
a substrate; a pillar vertically protruding from the substrate, the pillar comprising a lower impurity region and an upper impurity region therein and a vertical channel region therebetween, wherein a portion of the pillar including the lower impurity region therein includes a first mesa and a second mesa laterally extending therefrom; a bit line extending on the first mesa and on a first sidewall of the pillar and electrically contacting the lower impurity region, wherein the first mesa laterally extends in a direction perpendicular to the bit line, and wherein the bit line directly contacts the first mesa along a bottom surface thereof and directly contacts the lower impurity region along a sidewall thereof; a word line extending on the second mesa and on a second sidewall of the pillar that is perpendicular to the first sidewall and adjacent the vertical channel region, the word line linearly extending in the direction perpendicular to the bit line and spaced apart from the second mesa; and a gate insulating layer extending on the second sidewall between the vertical channel region and the word line, and between the second mesa and the word line.