| 摘要 |
PROBLEM TO BE SOLVED: To obtain an asynchronous data receiving circuit for receiving data correctly even when there is a deviation between a receive clock frequency and a system clock frequency inputted together with data.SOLUTION: The asynchronous data receiving circuit comprises: a clock phase determination unit 140 for determining proximity between the phase of the receive clock and the phase of a positive-phase clock synchronized to the system clock, and determining proximity between the phase of the receive clock and the phase of an inverse-phase clock 180 degrees out of phase with the system clock; a received data inverse-phase sampling unit 162 for sampling and latching received data with the positive-phase clock; and a data selector 190 for selecting output of the received data inverse-phase sampling unit 162 when the clock phase determination unit 140 determines proximity between the phase of the receive clock and the phase of the positive-phase clock, or selects output of a received data positive-phase sampling unit 161 when proximity between the phase of the receive clock and the phase of the inverse-phase clock is determined. |
