发明名称 |
METHOD AND SYSTEM FOR DESIGNING 3D SEMICONDUCTOR PACKAGE |
摘要 |
Provided is a method for designing a 3D semiconductor package, comprising the steps of providing a first layout parameter for a plurality of first terminals included in a first package, a second layout parameter for a plurality of second terminals included in a second package at an upper part or a lower part of the first package, and a third layout parameter for a plurality of connection terminals which electrically connect the first package to the second package; obtaining a first wire connection layout between a first and a second terminal and the connection terminals by applying a first algorithm to the first to the third layout parameter; and obtaining a second wire connection layout between the first and the second terminal and the connection terminals by applying a second algorithm, different from the first algorithm, to the first wire connection layout. |
申请公布号 |
KR20140093510(A) |
申请公布日期 |
2014.07.28 |
申请号 |
KR20130005996 |
申请日期 |
2013.01.18 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
HWANG, BO SUN;YUN, SUNG HEE;JEONG, JAE HOON;LEE, WON CHEOL;LEE, TAE HEON;CHEON, YOUNG HOE |
分类号 |
G06F17/50;G11C5/06 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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