发明名称 Cached PHY register data access
摘要 Ethernet physical sublayer (PHY) devices each provide PHY register data. One or more of the Ethernet PHY devices are connected to each of one or more management data input/output (MDIO)/management data clock (MDC) interfaces to which a number of MDIO/MDC controllers are connected. Each MDIO/MDC controller polls a corresponding MDIO/MDC interface to receive the PHY register data from the one or more Ethernet PHY devices connected thereto. The MDIO/MDC controllers store portions of the PHY register data received from the Ethernet PHY devices to a memory to which an interface is connected. A processor connected to the interface accesses the portions of the PHY register data stored to the memory. The processor can retrieve the portions of the PHY register data over the interface more quickly than the MDIO/MDC controllers can retrieve the PHY register data over the MDIO/MDC interfaces.
申请公布号 US2014207981(A1) 申请公布日期 2014.07.24
申请号 US201313745828 申请日期 2013.01.20
申请人 BUSINESS MACHINES CORPORATION INTERNATIONAL 发明人 Baker Anthony E.
分类号 G06F13/38 主分类号 G06F13/38
代理机构 代理人
主权项 1. A device comprising: a processor; one or more management data input/output (MDIO)/management data clock (MDC) interfaces to which the processor are not directly connected; a plurality of Ethernet physical sublayer (PHY) devices one or more Ethernet PHY devices of the Ethernet PHY devices connected to each MDIO/MDC interface, each Ethernet PHY device to provide PHY register data directly onto the MDIO/MDC interface to which the Ethernet PHY device is connected; a plurality of MDIO/MDC controllers separate from the processor, each MDIO/MDC controller connected to and to poll a corresponding MDIO/MDC interface of the MDIO/MDC interfaces to receive the PHY register data from the one or more Ethernet PHY devices connected to the corresponding MDIO/MDC interface; a memory to which the MDIO/MDC controllers are to store portions of the PHY register data received from the Ethernet PHY devices; and an interface separate from the MDIO/MDC interfaces and connecting the memory to the processor, the processor accessing the portions of the PHY register data stored to the memory to retrieve the PHY register data without having to poll the Ethernet PHY devices itself via the MDIO/MDC interfaces.
地址 US