| 摘要 |
A scheduling system for a packet processing system is disclosed, and can include a classification circuit connected to a memory bus and configurable to classify network packets, placing the classified network packets into first multiple input/output queues, a scheduling circuit for reordering the network packets received from the classification circuit through the first multiple input/output queues and placing the reordered network packets into second multiple input/output queues, an arbitration circuit for directing network packets received from the scheduling circuit through the second multiple input/output queues to multiple output ports, and multiple offload processors, each coupled to at least one of the multiple output ports, the offload processors configured to modify the network packets. |
