发明名称 |
INSTRUCTION SCHEDULING FOR A MULTI-STRAND OUT-OF-ORDER PROCESSOR |
摘要 |
In one embodiment, a multi-strand system with a pipeline includes a front-end unit, an instruction scheduling unit (ISU), and a back-end unit. The front-end unit performs an out-of-order fetch of interdependent instructions queued using a front-end buffer. The ISU dedicates two hardware entries per strand for checking operand-readiness of an instruction and for determining an execution port to which the instruction is dispatched. The back-end unit receives instructions dispatched from the hardware device and stores the instructions until they are executed. Other embodiments are described and claimed. |
申请公布号 |
US2014208074(A1) |
申请公布日期 |
2014.07.24 |
申请号 |
US201213993552 |
申请日期 |
2012.03.30 |
申请人 |
Babayan Boris A.;Pentkovski Vladimir;Iyer Jayesh;Kosarev Nikolay;Shishlov Sergey Y.;Butuzov Alexander V.;Sivtsov Alexey Y. |
发明人 |
Babayan Boris A.;Pentkovski Vladimir;Iyer Jayesh;Kosarev Nikolay;Shishlov Sergey Y.;Butuzov Alexander V.;Sivtsov Alexey Y. |
分类号 |
G06F9/30 |
主分类号 |
G06F9/30 |
代理机构 |
|
代理人 |
|
主权项 |
1. A method, comprising:
fetching a strand of interdependent instructions for execution, wherein the strand of interdependent instructions are fetched out of order; dedicating a first hardware resource and a second hardware resource for the strand; storing an instruction of the strand using the first hardware resource; determining whether the instruction stored using the first hardware resource is operand-ready; storing the instruction using the second hardware resource when the instruction is operand-ready; and determining an available execution port for the instruction stored using the second hardware resource. |
地址 |
Moscow RU |