| 摘要 |
<p>A static random access memory (SRAM) cell includes first (220) and second (228) n-channel transistors, first (224) and second (232) p-channel transistors, first (234) and second (238) enable transistors, and first (208) and second (212) pass gates. The first n-channel transistor (220), the first p-channel transistor (224), and the first enable transistor (234) are connected in series between first (240) and second (236) reference potentials. The second n- channel transistor (228), the second p-channel transistor (232), and the second enable transistor (238) are connected in series between the first (240) and second (236) reference potentials. The first pass gate (208) is configured to selectively connect a first bitline (BL) to a first node. The first node is connected to a gate of the first n-channel transistor (220) and a gate of the first p-channel transistor (224). The second pass gate (212) is configured to selectively connect a second bitline (BLB) to a second node. The second node is connected to a gate of the second n-channel transistor (228) and a gate of the second p-channel transistor (232). The gate of the first (234) and second (238) enable transistors are respectively controlled by the first (BL) and second (BLB) bit lines so as to avoid conflict or competition between the first (224) and second (232) p-channel transistors and the first (208) and second (212) pass gates during a write operation. The present application further discloses word line repeaters and pulsed word line operation during reading.</p> |
