发明名称 VECTOR PROCESSOR HAVING INSTRUCTION SET WITH VECTOR CONVOLUTION FUNCTION FOR FIR FILTERING
摘要 Maximum likelihood bit-stream generation and detection techniques are provided using the M-algorithm and Infinite Impulse Response (IIR) filtering. The M-Algorithm is applied to a target input signal X to perform Maximum Likelihood Sequence Estimation on the target input signal X to produce a digital bit stream B, such that after filtering by an IIR filter, the produced digital stream Y produces an error signal satisfying one or more predefined requirements. The predefined requirements comprise, for example, a substantially minimum error. In an exemplary bit detection implementation, the target input signal X comprises an observed analog signal and the produced digital stream Y comprises a digitized output of a receive channel corresponding to a transmitted bit stream. In an exemplary bit stream generation implementation, the target input signal X comprises a desired transmit signal and the produced digital stream Y comprises an estimate of the desired transmit signal.
申请公布号 KR20140092852(A) 申请公布日期 2014.07.24
申请号 KR20147014118 申请日期 2012.10.26
申请人 LSI CORPORATION 发明人 AZADET KAMERAN;YU MENG LIN;OTHMER JOSEPH H.;WILLIAMS JOSEPH;MOLINA ALBERT
分类号 G06F17/16;G06F9/06 主分类号 G06F17/16
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