发明名称 THREE-DIMENSIONAL QUANTUM WELL TRANSISTOR AND FABRICATION METHOD
摘要 Three dimensional quantum well transistors and fabrication methods are provided. A quantum well layer, a barrier layer, and a gate structure can be sequentially formed on an insulating surface of a fin part. The gate structure can be formed over the barrier layer and across the fin part. The QW layer and the barrier layer can form a hetero-junction of the transistor. A recess can be formed in the fin part on both sides of the gate structure to suspend a sidewall spacer. A source and a drain can be formed by growing an epitaxial material in the recess and the sidewall spacer formed on both sidewalls of the gate electrode can be positioned on surface of the source and the drain.
申请公布号 US2014203243(A1) 申请公布日期 2014.07.24
申请号 US201314144623 申请日期 2013.12.31
申请人 Semiconductor Manufacturing International (Shanghai) Corporation 发明人 XIAO DE YUAN
分类号 H01L29/66;H01L29/15;H01L29/267;H01L29/78 主分类号 H01L29/66
代理机构 代理人
主权项 1. A method for forming a transistor comprising: providing a semiconductor substrate; forming a buffer layer on the semiconductor substrate; forming a fin part by etching the buffer layer, wherein the fin part is formed of an insulating material; forming an insulating layer on the semiconductor substrate, the insulating layer having a top surface lower than a top surface of the fin part; forming a quantum well (QW) layer on surface of the fin part; forming a barrier layer on surface of the QW layer; forming a gate structure on the barrier layer across the fin part and on the insulating layer, the gate structure including a gate dielectric layer on each of the insulating layer and the barrier layer, and a gate electrode on the gate dielectric layer; forming a sidewall spacer on both sidewalls of the gate structure; forming a recess in the fin part on both sides of the gate structure to suspend the sidewall spacer; and forming a source and a drain by growing an epitaxial material in the recess, each of the source and the drain including a side edge aligned with a sidewall edge of the gate structure such that a channel region in the QW layer under the gate structure having a same width with the gate structure and the channel region does not extend to under the sidewall spacer.
地址 Shanghai CN