Wire-Last Integration Method and Structure for III-V Nanowire Devices

摘要

In one aspect, a method of fabricating a nanowire FET device includes the following steps. A layer of III-V semiconductor material is formed on an SOI layer of an SOI wafer. Fins are etched into the III-V material and SOI layer. One or more dummy gates are formed over a portion of the fins that serves as a channel region of the device. A gap filler material is deposited onto the wafer. The dummy gates are removed selective to the gap filler material, forming trenches in the gap filler material. The SOI layer is removed from portions of the fins within the trenches thereby forming suspended nanowire channels in the channel regions of the device. The trenches are filled with at least one gate material to form one or more replacement gates surrounding the nanowire channels in a gate-all-around configuration.

主权项

1. A method of fabricating a nanowire field-effect transistor (FET) device, the method comprising the steps of:
providing a semiconductor-on-insulator (SOI) wafer having an SOI layer over a buried oxide (BOX); forming a layer of III-V semiconductor material on the SOI layer; etching fins into the III-V semiconductor material and the SOI layer; forming a dummy gate dielectric on the fins; forming one or more dummy gates over a portion of the fins that serves as a channel region of the device, wherein the dummy gates are separated from the fins by the dummy gate dielectric; forming spacers on opposite sides of the dummy gates; depositing a gap filler material onto the wafer filling spaces between the fins and the dummy gates; removing the dummy gates and the dummy gate dielectric selective to the gap filler material, forming trenches in the gap filler material; removing the SOI layer from portions of the fins within the trenches thereby forming suspended nanowire channels in the channel regions of the device, wherein portions of the fins outside of the trenches will serve as source and drain regions of the device; and filling the trenches with at least one gate material to form one or more replacement gates surrounding the nanowire channels in a gate-all-around configuration.