ANALOG-TO-DIGITAL CONVERSION IN PIXEL ARRAYS

摘要

An analog-to-digital converter for generating an output digital value equivalent to the difference between a first analog signal level (Vres) and a second analog signal level (Vsig) comprises at least one input for receiving the first analog signal level and the second analog signal level, an input for receiving a ramp signal and an input for receiving at least one clock signal. A set of N counters, where N≧2, are arranged to use N clock signals which are offset in phase from one another. A control stage is arranged to enable the N counters based on a comparison of the ramp signal with the first analog signal level (Vres) and the second analog signal level (Vsig). An output stage is arranged to output the digital value which is a function of values accumulated by the N counters during a period when they are enabled.

主权项

1. An analog-to-digital converter for generating an output digital value equivalent to the difference between a first analog signal level and a second
analog signal level comprising: at least one input for receiving the first analog signal level and the second analog signal level;
an input for receiving a ramp signal;an input for receiving at least one clock signal;a set of N counters, where N≧2, wherein the N counters are arranged to use N clock signals which are offset in phase from one another; a control stage which is arranged to enable the N counters based on a comparison of the ramp signal with the first analog signal level and the second analog signal level; and an output stage for outputting the digital value which is a function of values accumulated by the N counters during a period when they are enabled.