INTEGRATED CIRCUITS AND METHODS FOR DYNAMIC FREQUENCY SCALING

摘要

In an integrated circuit, a first delay locked loop circuit is configured to adjust a phase of a first clock signal input to a first clock input terminal, and to at least one of transmit and receive information based on the phase-adjusted first clock signal. A second delay locked loop circuit is configured to adjust a phase of a second clock signal input to a second clock input terminal, and to at least one of transmit and receive information based on the phase-adjusted second clock signal. A path selection circuit is configured to select, in response to a select signal, one of a first signal path through the first delay locked loop circuit and a second signal path through the second delay locked loop circuit as a signal path for at least one of transmitting and receiving the information.

主权项

1. A method for dynamic frequency scaling in a memory system, the method comprising:
adjusting a phase of a first clock signal by supplying the first clock signal to a first delay locked loop circuit in a standby state; and changing, after the first delay locked loop circuit in the standby state reaches a lock state, a signal path for transmitting information between a memory controller and a memory device from a second signal path through a second delay locked loop circuit to which a second clock signal is supplied to a first signal path through the first delay locked loop circuit in the standby state during a period in which no information is transmitted between the memory controller and the memory device.