发明名称 |
PHASE COMPARISON CIRCUIT AND DATA RECEIVING UNIT |
摘要 |
A phase comparison circuit includes: a first flip-flop configured to receive a data signal and a clock signal; a second flip-flop configured to receive an output signal of the first flip-flop and a signal that is an inversion of logic of the clock signal; a delay circuit configured to give delay time to the data signal, in which the delay time is equal to or longer than signal delay time from a clock terminal of the first flip-flop to a Q output terminal of the first flip-flop; a first exclusive OR circuit configured to receive an output signal of the delay circuit and the output signal of the first flip-flop; and a second exclusive OR circuit configured to receive the output signal of the first flip-flop and an output signal of the second flip-flop. |
申请公布号 |
US2014203842(A1) |
申请公布日期 |
2014.07.24 |
申请号 |
US201414156770 |
申请日期 |
2014.01.16 |
申请人 |
Sony Corporation |
发明人 |
Maruko Kenichi |
分类号 |
H03K3/012 |
主分类号 |
H03K3/012 |
代理机构 |
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代理人 |
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主权项 |
1. A phase comparison circuit, comprising:
a first flip-flop configured to receive a data signal and a clock signal; a second flip-flop configured to receive an output signal of the first flip-flop and a signal that is an inversion of logic of the clock signal; a delay circuit configured to give delay time to the data signal, the delay time being equal to or longer than signal delay time from a clock terminal of the first flip-flop to a Q output terminal of the first flip-flop; a first exclusive OR circuit configured to receive an output signal of the delay circuit and the output signal of the first flip-flop; and a second exclusive OR circuit configured to receive the output signal of the first flip-flop and an output signal of the second flip-flop. |
地址 |
Tokyo JP |