| 摘要 |
Compression and decompression of numerical data utilizing single instruction, multiple data (SIMD) instructions is described. The numerical data includes integer and floating-point samples. Compression supports three encoding modes: lossless, fixed-rate, and fixed-quality. SIMD instructions for compression operations may include attenuation, derivative calculations, bit packing to form compressed packets, header generation for the packets, and packed array output operations. SIMD instructions for decompression may include packed array input operations, header recovery, decoder control, bit unpacking, integration, and amplification. Compression and decompression may be implemented in a microprocessor, digital signal processor, field-programmable gate array, application-specific integrated circuit, system-on-chip, or graphics processor, using SIMD instructions. Compression and decompression of numerical data can reduce memory, networking, and storage bottlenecks. This abstract does not limit the scope of the invention as described in the claims. |
| 主权项 |
1. A computer system, comprising:
a data processor and memory accessible by the data processor, the memory storing computer programs executable by the data processor, including at least one application program and a set of functions to implement operations to perform compression of data samples from a data set, the at least one application program and the set of functions including single instruction multiple data (SIMD) instructions for at least a portion of the operations to be executed by the data processor, the data processor including a set of registers; a first register of the register set to store a plurality of operands corresponding to an encoding group of data samples; an exponent register of the register set, the data processor responsive to a SIMD instruction for operations to determine a maximum exponent value of the plurality of operands in the first register and to store the maximum exponent value in the exponent register; interleaver logic to interleave bits of the operands in the first register to produce a plurality of nibbles to store in a second register of the register set, wherein the interleaver logic maps the bits to a given nibble based on a place value of the bits in respective operands; a third register of the register set, the data processor responsive to a SIMD instruction for operations to select a subset of nibbles from the plurality of nibbles in the second register to store in the third register, wherein a number of nibbles for the subset is based on the maximum exponent value, wherein the subset of nibbles includes interleaved mantissa bits of the operands; and logic to pack the interleaved mantissa bits of the subset of nibbles from the third register to a compressed data packet, wherein the packed interleaved mantissa bits represent compressed data for the encoding group of data samples. |
