发明名称 |
PROVIDING HARDWARE SUPPORT FOR SHARED VIRTUAL MEMORY BETWEEN LOCAL AND REMOTE PHYSICAL MEMORY |
摘要 |
In one embodiment, the present invention includes a memory management unit (MMU) having entries to store virtual address to physical address translations, where each entry includes a location indicator to indicate whether a memory location for the corresponding entry is present in a local or remote memory. In this way, a common virtual memory space can be shared between the two memories, which may be separated by one or more non-coherent links. Other embodiments are described and claimed. |
申请公布号 |
US2014208042(A1) |
申请公布日期 |
2014.07.24 |
申请号 |
US201414221741 |
申请日期 |
2014.03.21 |
申请人 |
Chinya Gautham N.;Wang Hong;Mathaikutty Deepak A.;Collins Jamison D.;Schuchman Ethan;Held James P.;Bhatt Ajay V.;Sethi Prashant;Whalley Stephen F. |
发明人 |
Chinya Gautham N.;Wang Hong;Mathaikutty Deepak A.;Collins Jamison D.;Schuchman Ethan;Held James P.;Bhatt Ajay V.;Sethi Prashant;Whalley Stephen F. |
分类号 |
G06F12/10;G06F12/12 |
主分类号 |
G06F12/10 |
代理机构 |
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代理人 |
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主权项 |
1. A processor comprising:
a first core including a first memory management unit (MMU), the first MMU including a plurality of entries to store virtual address to physical address translations; and an accelerator coupled to the first core and including a second MMU, the second MMU including a plurality of entries to store virtual address to physical address translations, wherein each entry of the first MMU includes a location field to store a first indicator to indicate whether a memory location for the corresponding entry is present in a first memory coupled to the processor or in a second memory coupled to the accelerator and an identifier field to store an identifier of the accelerator, wherein the processor is to execute a handler to convert a memory request for a memory location in the second memory to a direct memory access (DMA) transaction for communication to the second memory. |
地址 |
Hillsboro OR US |