发明名称 |
SOURCE SYNCHRONOUS BUS SIGNAL ALIGNMENT COMPENSATION MECHANISM |
摘要 |
An apparatus having a bit lag control element that measures a propagation time beginning with assertion of a first signal and ending with assertion of a second signal, and that generates a first value indicating an adjusted propagation time. The control element includes delay lock control, adjust logic, and a gray encoder. The delay lock control selects one of a plurality of successively delayed versions of the first signal that coincides with the assertion the second signal, and generates a second value on a lag select bus that indicates the propagation time. The adjust logic is coupled to a circuit and to the lag select bus, and adjusts the second value by an amount prescribed by the circuit to yield a third value that is output to an adjusted lag bus. The gray encoder gray encodes the third value to generate the first value on the lag bus. |
申请公布号 |
US2014204691(A1) |
申请公布日期 |
2014.07.24 |
申请号 |
US201313747187 |
申请日期 |
2013.01.22 |
申请人 |
VIA TECHNOLOGIES, INC. |
发明人 |
Canac Vanessa S.;Lundberg James R. |
分类号 |
H03K5/159 |
主分类号 |
H03K5/159 |
代理机构 |
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代理人 |
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主权项 |
1. An apparatus that compensates for misalignment on a synchronous data bus, the apparatus comprising:
a bit lag control element, configured to measure a propagation time beginning with assertion of a first signal and ending with assertion of a second signal, and configured to generate a first value on a lag bus that indicates an adjusted propagation time, said bit lag control element comprising:
delay lock control, configured to select one of a plurality of successively delayed versions of said first signal that coincides with said assertion said second signal, and configured to generate a second value on a lag select bus that indicates said propagation time;adjust logic, coupled to a circuit and to said lag select bus, configured adjust said second value by an amount prescribed by said circuit to yield a third value that is output to an adjusted lag bus; anda gray encoder, configured to gray encode said third value to generate said first value on said lag bus. |
地址 |
New Taipei City TW |