| 摘要 |
In a multiple port SRAM (10), a first bit cell (38) is coupled to first and second word lines (WL0A/WL0B) and first (BL0A/BL0Ab) and second bit line pairs (BL0B/BL0Bb). A first data line pair (DLA/DLAb) is coupled to the first bit line pair (BL0A/BL0Ab) via first switching logic (52, 54). A second data line pair (DLB, DLBb) is coupled to the first bit line pair via second switching logic (56, 58) and to the second bit line pair via third switching logic (60, 62). If a row address match but not a column address match exists between first and second access addresses, the second switching logic selectively connects the second data line pair to the first bit line pair based on a first decoded signal generated from a column address of the second access address and the third switching logic decouples the second data line pair from the second bit line pair. |
