发明名称 |
Synthesizer with lock detector and method of operation thereof |
摘要 |
The present invention provides an apparatus and method for generating a lock detect signal indicative of stability of a frequency of an output signal based upon UP and DN signals received from a phase detector. The apparatus comprises an input that receives the UP and DN signals; a first circuit that combines the received UP and DN signals to obtain a combined signal; a delay stage that operates upon the combined signal to obtain a delayed combined signal; and a second circuit that operates upon the combined signal and the delayed combined signal to obtain the lock detect signal. |
申请公布号 |
EP2757692(A2) |
申请公布日期 |
2014.07.23 |
申请号 |
EP20140165271 |
申请日期 |
2001.12.17 |
申请人 |
QUALCOMM INCORPORATED |
发明人 |
SU, DAVID, K.;YUE, CHIK, PATRICK;WEBER, DAVID, J.;ZARGARI, MASOUD |
分类号 |
H03L7/095;H03K23/66;H03L7/089;H03L7/099;H03L7/10;H03L7/183;H03L7/193 |
主分类号 |
H03L7/095 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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