Generating data feed specific parser circuits

摘要

Generating a data feed specific parser circuit is provided. An input of a number of bytes of feed data associated with a particular data feed that the data feed specific parser circuit is to process is received. A feed format specification file that describes a data format of the particular data feed is parsed to generate an internal data structure of the feed format specification file. A minimum number of parallel pipeline stages in the data feed specific parser circuit to process the number of bytes of feed data associated with the particular data is determined based on the generated internal data structure of the feed format specification file. Then, a description of the data feed specific parser circuit with the determined number of parallel pipeline stages is generated.

主权项

1. A computer implemented method for generating a data feed specific parser circuit, the computer implemented method comprising:
receiving, by the computer, an input of a number of bytes of feed data associated with a particular data feed that the data feed specific parser circuit is to process; parsing, by the computer, a feed format specification file that describes a data format of the particular data feed using a compiler to generate an internal data structure of the feed format specification file; determining, by the computer, a minimum number of parallel pipeline stages in the data feed specific parser circuit to process the number of bytes of feed data associated with the particular data feed in parallel during a hardware clock cycle based on the generated internal data structure of the feed format specification file; determining, by the computer, a minimum memory contents and block size in the data feed specific parser circuit to process the number of bytes of feed data associated with the particular data feed in parallel during the hardware clock cycle based on the generated internal data structure of the feed format specification file; generating, by the computer, a description of the data feed specific parser circuit with the determined minimum number of parallel pipeline stages; and configuring, by the computer, a configurable hardware chip using the generated description of the data feed specific parser circuit with the determined minimum number of parallel pipeline stages and the determined minimum memory contents and block size to process the number of bytes of feed data associated with the particular data feed in parallel per hardware clock cycle.