发明名称 Serial memory and IO access architecture and system for switched telecommunication and computing platforms
摘要 A computing and communication architecture utilizes a serial protocol based switched fabric among circuit cards housed in packaging arrangement. In one embodiment, each circuit card connected to the serial protocol based switched fabric in the packaging arrangement is provided with a protocol processor that enables all of the circuit cards to efficiently provide packet-based serial self-clocked communications at line speed. As a result, it is not necessary to arrange the circuit cards in a hierarchical manner in order to address the problems of switch blocking and related traffic congestion issues that would otherwise limit the implementation of the serial protocol based backplane arrangement for housing circuit cards.
申请公布号 US8787364(B2) 申请公布日期 2014.07.22
申请号 US201213421826 申请日期 2012.03.15
申请人 发明人 Sharma Viswa Nath;Stuck Barton W.;Hu Ching-Tai;Chou Yi-chang;Chu William
分类号 H04L12/50 主分类号 H04L12/50
代理机构 代理人
主权项 1. A computing and communication apparatus adapted for interconnection to the Internet, the apparatus comprising: a plurality of circuit cards which use packet frame switched full duplex serial communication for all external communications of the cards including memory and input/output accesses; and, a communication fabric providing packet frame switched full duplex serial communication over a backplane via a serial packet frame switching device to the said circuit cards; and, the said circuit cards and the said communication fabric are housed in a packaging arrangement; and, each of the said circuit cards is communicably interconnected via the said communication fabric serial packet frame switching device; and, each of the said circuit cards is communicably interconnected to the Internet via the said serial packet frame switching device; and, at least one of the said circuit cards includes a protocol processor which encapsulates the memory and input/output access including instruction access of the circuit card to serial packet frame to provide full duplex serial packet-based communication for the circuit card over the backplane at a speed in excess of one gigabits per second.
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