Post-gate shallow trench isolation structure formation

摘要

Doped wells, gate stacks, and embedded source and drain regions are formed on, or in, a semiconductor substrate, followed by formation of shallow trenches in the semiconductor substrate. The shallow trenches can be formed by forming a planarized material layer over the doped wells, the gate stacks, and the embedded source and drain regions; patterning the planarized material layer; and transferring the pattern in the planarized material layer into the gate stacks, embedded source and drain regions, and the doped wells. The shallow trenches are filled with a dielectric material to form shallow trench isolation structures. Alternately, the shallow trenches can be formed by applying a photoresist over the doped wells, the gate stacks, and the embedded source and drain regions, and subsequently etching exposed portions of the underlying structures. After removal of the photoresist, shallow trench isolation structures can be formed by filling the shallow trenches.

主权项

1. A method of forming a semiconductor structure comprising:
forming a gate stack including a gate dielectric and a gate electrode on a semiconductor substrate; removing end portions of said gate electrode by an anisotropic etch, wherein two sidewalls of said gate electrode that become physically exposed during said anisotropic etch are vertically coincident with sidewalls of one of at least one semiconductor portion; forming, after removing said end portions of said gate electrode, a trench laterally surrounding a contiguous set of said at least one semiconductor portion in said semiconductor substrate after forming said gate stack; and filling said trench with a dielectric material, wherein a shallow trench isolation structure comprising at least a dielectric material portion embedded in said semiconductor substrate and laterally surrounding said contiguous set of said at least one semiconductor portion is formed.