发明名称 Wafer level packaging using a lead-frame
摘要 Wafer level packaging using a lead-frame. When used to package two or more chips, a final product having QFN package-like finish. The final product will also have a performance rivaling or exceeding that of a corresponding monolithic chip because of the very close connection of the two or more chips and the ability to tailor the fabrication processing of each chip to only that required for the devices on that chip. The wafer level packaging can also be used to package monolithic chips, as well as chips having active devices on one chip and passive devices on a second chip. Various exemplary embodiments are disclosed.
申请公布号 US8785244(B2) 申请公布日期 2014.07.22
申请号 US201213689416 申请日期 2012.11.29
申请人 Maxim Integrated Products, Inc. 发明人 Ashrafzadeh Ahmad R.
分类号 H01L21/56 主分类号 H01L21/56
代理机构 Blakely Sokoloff Taylor & Zafman LLP 代理人 Blakely Sokoloff Taylor & Zafman LLP
主权项 1. A method of wafer level packaging comprising: a) fabricating a first wafer with a repetitive matrix of first circuits thereon and having a corresponding pattern of circuit contacts formed by a plurality of redistribution layers accessible from a first surface thereof; b) fabricating a lead frame matrix having a repetitive pattern of lead frames and lead frame portions for electrically connecting to the circuit contacts on the first wafer, each lead frame including a plurality of lead frame portions extending toward each other from opposite sides of the lead frame, the lead frame portions extending less than half way across the lead frame so that tips of lead frame portions from one side of the lead frame do not extend between tips of the lead frame portions from the other side of the lead frame; c) electrically connecting the lead frame portions on the lead frame matrix to the circuit contacts on the first wafer; etching the lead frame matrix to separate the lead frame portions; d) dicing the first wafer.
地址 San Jose CA US