| 发明名称 | N-well switching circuit | ||
| 摘要 | A dual-mode PMOS transistor is disclosed that has a first mode of operation in which a switched n-well for the dual-mode PMOS transistor is biased to a high voltage. The dual-mode PMOS transistor has a second mode of operation in which the switched n-well is biased to a low voltage that is lower than the high voltage. The dual-mode PMOS transistor has a size and gate-oxide thickness each having a magnitude that cannot accommodate a permanent tie to the high voltage. An n-well voltage switching circuit biases the switched n-well to prevent voltage damage to the dual-mode PMOS transistor despite its relatively small size and thin gate-oxide thickness. | ||
| 申请公布号 | US8787096(B1) | 申请公布日期 | 2014.07.22 |
| 申请号 | US201313742964 | 申请日期 | 2013.01.16 |
| 申请人 | QUALCOMM Incorporated | 发明人 | Terzioglu Esin;Uvieghara Gregory Ameriada;Yoon Sei Seung;Ganesan Balachander;Kota Anil Chowdary |
| 分类号 | G11C7/00;G11C13/00 | 主分类号 | G11C7/00 |
| 代理机构 | Haynes and Boone, LLP | 代理人 | Haynes and Boone, LLP |
| 主权项 | 1. A voltage switching circuit, comprising: an NMOS transistor having a gate controlled responsive to a control signal, a drain coupled to a low-voltage supply configured to provide a low voltage, and a source coupled to a switched n-well for a dual-mode PMOS transistor; and a first PMOS transistor having a gate controlled responsive to the control signal, a source coupled to a high-voltage supply configured to provide a high voltage that is greater than the low voltage, and a drain coupled to the switched n-well. | ||
| 地址 | San Diego CA US | ||