Liquid crystal display device having output transistor having large capacitor component

摘要

The liquid crystal display device includes an output portion which is configured to include an output transistor having a large capacitor component. The output portion includes a top electrode which is configured to include an output transistor having a large capacitor component. As such, the liquid crystal display device can enhance the response speed of liquid crystal.

主权项

1. A liquid crystal display device comprising:
a display panel configured to display an image and include a plurality of gate lines and a plurality of data lines arranged on it; a data driver configured to supply the data lines of the display panel with data signals corresponding to the image; and a gate driver disposed on the display panel and configured to include a plurality of shift registers which are configured to apply output signals sequentially shifted from a start pulse to the gate lines, each of the shift registers including a control portion having first to seventh transistors and an output portion having eighth and ninth transistors: wherein the control portion includes the first transistor which responds to the start pulse and is connected between an input line for a gate high voltage and a first node; the second transistor which responds to the output signal and is connected between the first node and an input line for gate low voltage; the third transistor which responds to a voltage from a second node and is connected between a drain electrode of the first transistor and the input line for the gate low voltage; the fourth transistor which responds to the output signal and is connected between the input line of the gate high voltage and a source electrode of the fifth transistor; the fifth transistor which responds to the voltage on the first node and is connected between a drain electrode of the fourth transistor and the input line for the gate low voltage; the sixth transistor which responds to the gate high voltage and is connected between the input line of the gate high voltage and the second node; and the seventh transistor which responds to the start pulse and is connected between the second node and the input line of the gate low voltage, wherein the output portion includes: the eighth transistor which selectively applies a clock signal to the gate line according to the voltage on the first node; and the ninth transistor which selectively discharges the voltage on the gate line according to the voltage on the second node, wherein the eighth transistor includes:
a gate electrode responsive to a voltage on the first node;a source electrode receiving the clock signal; a drain electrode connected to the respective gate line and configured to apply the clock signal from the source electrode of the eighth transistor to the respective gate line according to the voltage on the first node;
a semiconductor layer disposed opposite the gate electrode;a passivation layer disposed on the source and drain electrodes of the eighth transistor;a top electrode disposed on the passivation layer and electrically connected to the gate electrode through a contact hole through the passivation layer, anda control portion controlling the output portion, wherein a first capacitor component is generated between the gate electrode and one of the source electrode of the eighth transistor and the drain electrode of the eighth transistor, and wherein a second capacitor component is generated between the top electrode and one of the source electrode of the eighth transistor and the drain electrode of the eighth transistor.