发明名称 |
Chip package and method for forming the same |
摘要 |
According to an embodiment, a chip package is provided, which includes: a substrate having a first surface and a second surface; a device region formed in the substrate; a passivation layer formed overlying the first surface of the substrate; at least a polymer planarization layer formed overlying the passivation layer; a package substrate disposed overlying the first surface of the substrate; and a spacer layer disposed between the package substrate and the passivation layer, wherein the spacer layer and the package substrate surround a cavity overlying the substrate, wherein the polymer planar layer does not extends to an outer edge of the spacer layer. |
申请公布号 |
US8785247(B2) |
申请公布日期 |
2014.07.22 |
申请号 |
US201313893015 |
申请日期 |
2013.05.13 |
申请人 |
|
发明人 |
Huang Yu-Lung;Huang Yu-Ting |
分类号 |
H01L21/44;H01L21/48;H01L21/50 |
主分类号 |
H01L21/44 |
代理机构 |
Liu & Liu |
代理人 |
Liu & Liu |
主权项 |
1. A method for forming a chip package, comprising:
providing a substrate having a first surface and a second surface, wherein a plurality of device regions are formed in the substrate, and the device regions are separated from each other by a plurality of predetermined scribe lines; forming a passivation layer on the first surface of the substrate; forming a polymer planar layer on the passivation layer; patterning the polymer planar layer to form a plurality of patterned polymer planar layers, wherein the patterned polymer planar layers are located on a corresponding one of the device regions, respectively; disposing a package substrate on the first surface of the substrate; disposing a spacer layer between the package substrate and the passivation layer, wherein the spacer layer and the package substrate surround a plurality of cavities on the substrate, and each of the patterned polymer planar layers does not extends to any one of the predetermined scribe lines, respectively; and dicing the substrate and the package substrate along the predetermined scribe lines to form a plurality of separate chip packages. |
地址 |
|