Digital re-sampling apparatus using fractional delay generator

摘要

Disclosed herein is a digital re-sampling apparatus. The digital re-sampling apparatus includes a sample buffer, a sample buffer control unit, a filter bank, a first delay bank, a fractional delay constant table, a combiner bank, and a second delay bank. The sample buffer temporarily stores an input sample in synchronization with an input sampling frequency. The sample buffer control unit controls writing and reading operations. The filter bank includes a number of digital filters equal to the number of stages, and filters the input sample. The first delay bank differentially delays a filter output value. The fractional delay constant table stores information about re-sampling time. The combiner bank includes a number of adders and multipliers, performs an operation, and outputs a re-sampled value. The second delay bank causes a delay so that output of each combiner can be synchronized with each output of the fractional delay constant table.

主权项

1. A digital re-sampling apparatus using a fractional delay generator, comprising:
a sample buffer for temporarily storing an input sample in synchronization with an input sampling frequency; a sample buffer control unit for controlling writing and reading operations of the sample buffer; a filter bank for digitally filtering the input sample, and comprising multiple digital filters composed of multiple taps, as many as stages in the filter bank; a first delay bank for differentially delaying each output of the multiple digital filters in the filter bank based on a number of the stages; a fractional delay constant table for storing information on time for re-sampling of the input sample; a combiner bank for generating a re-sampled output for every re-sampling time through arithmetic operations performed with the output of the first delay bank and a fractional delay constant stored in the fractional delay constant table, and comprising combiners composed of combinations of adders and multipliers, as many as the stages; and a second delay bank for synchronizing outputs of the combiners and outputs of the fractional delay constant table and delaying outputs of the combiners and outputs of the fractional delay constant table so as to obtain sequential high-speed operation of the combiners in the combiner bank.